This invention relates generally to charge coupled devices (CCD's) and more particularly to two-phase buried-channel charge coupled devices.
As is known in the art, charge coupled devices generally include a plurality of gates disposed over the surface of a semiconductor substrate intermediate an input (or source) region and an output (or drain) region formed in the substrate. In response to proper phasing and clocking of the gates electric charge introduced into the source region is shifted, unidirectionally, parallel to the surface of the substrate until the charge is removed at the drain region. The charge is shifted in well defined spatial intervals, called cells, and temporal intervals, called clock periods. Generally charge coupled devices may be characterized by two features, one related to the clocking or phasing (namely two-, three- or four-phase structures) and one relating to the location in the substrate of the charge transport (namely surface channel structure or buried channel structure).
Two-phase charge coupled devices have the minimum circuit complexity. In such devices two sets of interleaved gate electrodes are generally used, one such set of gate electrodes being clocked with signals which are out-of-phase with the signals clocking the other set of gate electrodes. In one two-phase surface-channel device each gate electrode is made up of two sections, a first one of such sections being formed on an oxide layer formed over the substrate which is thicker than the oxide layer over which a second one of such sections is formed. In this way the electrical potential under the second one of such sections will be higher than the electrical potential under the first one of the sections of the gate electrodes. Therefore, while each section of the gate electrode is coupled to the same clocking signal, two different electrical potentials are produced under each one of the sections of such gate electrode. In the process of shifting charge is first introduced into the portion of the substrate disposed beneath the first section of the gate electrode (such section sometimes being referred to as the "transfer well") and such charge is then transferred to the portion of the substrate disposed beneath the second section of the gate electrode (such section sometimes being referred to as the "storage well").
In another type of two-phase surface-channel coupled device each gate electrode is formed in two steps. Here the sections of the gate electrodes disposed over the storage wells are first formed in spaced relationship over an oxide formed over the surface of a p-type silicon substrate. These sections of the gate electrodes are used as an ion implantation mask and boron ions are thereby ion implanted into the portions of the silicon substrate disposed between adjacent ones of the formed sections of gate electrodes thereby providing enhanced p-type doping for the transfer wells, the enhanced additional p-type dopant reducing the electrical potential in the substrate relative to the potential in the storage wells. The second sections of the gate electrodes are then formed over the doped transfer wells.
In order to improve the speed and charge transfer efficiency of the charge coupled device the fringing electric field between gate electrodes of adjacent cells, specifically its component along the surface of the substrate, is utilized to speed up the transport of charge carriers by forming a charge transport channel beneath the surface of the substrate. Beneath the surface the electric field parallel to the substrate surface is stronger than at the surface. The two-phase buried channel charge coupled device therefore combines the advantage of minimum circuit complexity and high speed of operation with minimum charge loss during charge transport between adjacent cells. One common method to produce a two-phase buried-channel device includes forming the gate electrodes in two sections, the sections disposed over the storage wells being formed first over a p-type silicon substrate having an n-type doped buried channel formed therein. The n-type buried channel has a concentration consistent with that desired for the storage wells. These sections of the gate electrodes, which are disposed over the storage wells, are used as an ion implantation mask and a p-type dopant, such as boron, is implanted into the portions of the n-type buried channel which are disposed under the spaces between the sections of the gate electrodes first formed. The p-type dopant is implanted at a concentration to partially compensate the n-type dopant in the buried channel region, thereby forming the transfer wells of the device. The second portions of the gate electrodes are then formed over the transfer wells.
While such method is customarily used to produce two-phase buried channel devices, the difficulty in controlling the partially compensated doping limits reproducibility on a production basis since, for example, a complete annihilation of the n-type channel regions by the p-type dopant will destroy the buried channel. Further, the use of a compensation dopant increases the amount of total n-type and p-type dopant in the transfer wells and hence increases physical damage to the substrate, thereby creating increased numbers of trapping states (or centers) and recombination centers which degrade the charge transfer characteristics and so-called "dark current" of the device with concomitant reduction in operating speed and storage times. Further, when the n-type buried channel is formed using a shallow epitaxial n-type layer (having a thickness in the order of 2000-6000 A) over the surface of a p-type silicon substrate the crystallographic characteristics of such epitaxial layer are not as perfect as those of the substrate, thereby reducing the speed and increasing the "dark current" of the device. Further, out diffusion of impurities in the substrate into the epitaxial layer may reduce the efficiency of the device. While such buried channel may be formed using an n-type ion implantation prior to the formation of the first sections of the gate electrodes, the control of a p-type implantation to properly partially compensate the n-type dopant in the transfer wells becomes extremely difficult since it is desirable that the p-type dopant have nearly the same distribution profile in depth as the n-type dopant and that the partially compensated doping profile is easily predictable and insensitive to fluctuations in processing conditions. However, since different dopants are used, each with a different implantation level requirement and different implant distributions, and because such different dopants will diffuse differently during subsequent heating cycles, as annealing and oxidation, proper partial compensation over the entire depth of the buried channel does not occur. Still further, complications arise because the n-type dopant and p-type dopant may adversely influence each other during the diffusion and, in addition, may exhibit different degrees of activation after the subsequent heating cycles.